Field of the Invention
The present disclosure relates to electronic-design-automation (EDA) techniques. More specifically, the present disclosure relates to a technique for interacting with an integrated circuit in a hierarchical design.
Related Art
As semiconductor technology is scaled to ever smaller dimensions, there are commensurate increases in the complexity of digital circuit designs. For example, smaller dimensions typically result in digital circuit designs having an increased number of logic gates and time domains. Moreover, this increase in complexity typically results in a significant increase in the time and cost needed to design and implement digital circuits.
In Integrated Circuit (IC) Physical Design, the shapes and other geometric objects that are used to represent the mask data have physical coordinates expressed in a Cartesian plane. When the designs are hierarchical, each level of physical hierarchy has its own coordinate system. When viewed from the top level of a hierarchical design, lower-level shapes must be transformed in order to understand their location from the point of view of the top block. Users and algorithms that manipulate physical data across these hierarchy boundaries must go through the tedious task of transforming data, sometimes multiple times, as it is being changed.
Accordingly, what is desired are improved methods and apparatus for solving some of the problems discussed above. Additionally, what is desired are improved methods and apparatus for reducing some of the drawbacks discussed above.